In order to realize a high-speed performance and size reduction of semiconductor devices, such as a MISFET (metal insulator semiconductor field effect transistor), a thin gate dielectric layer has been adopted. However, a problem that gate leakage current increases when the thickness of a silicon oxide film and a silicon oxynitride film (hereinafter referred to as “a silicon oxide film and the like”) is reduced. The silicon oxide film and the like have been used as gate dielectric layers. To solve this problem, there has been proposed a technique which involves adopting a film having high dielectric constant (k) (hereinafter referred to as “a high-k gate dielectric layer”) as a gate dielectric layer.
Also, there has been proposed a technique which involves controlling the threshold voltage of a MOS (metal oxide semiconductor) transistor by forming P-type impurity regions (refer to, for example, Japanese Patent Laid-Open No. 2002-313950).
However, as a result of an examination by the present inventor, it became apparent that the use of a high-k gate dielectric layer as a gate dielectric layer of a MISFET causes the problem that the threshold voltage of a MISFET rises more than when a silicon oxide film and the like are used. As one cause, it might be that this is because the metals contained in a high-k gate dielectric layer and the Si contained in a gate electrode react with each other. Furthermore, as another cause it might be that this is because the metals contained in a high-k gate dielectric layer react with arsenic ions and boron ions implanted into a substrate for use in the formation of source/drain regions.
Since the driving performance of a transistor decreases if the threshold voltage of a MISFET rises, it is necessary to control the threshold voltage with high accuracy.